The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device which is electrically programmable and erasable.
As a hitherto known method of manufacturing a nonvolatile semiconductor memory device of the type mentioned above, there may be mentioned a method disclosed, for example, in JP-A-56-142675. This known nonvolatile semiconductor memory device manufacturing method is directed to reduction in size of memory cells constituting the nonvolatile semiconductor memory device, which will be reviewed below.
According to this known method, three layers including a gate oxide film, a first polysilicon layer and a nitride film are deposited on a silicon substrate surface, whereon these layers are patterned with stripe-like columnwise lines (i.e., they are formed with a pattern of stripe-like lines extending in the columnwise direction) through a so-called patterning process. In succession, n-type impurity ions are implanted in the semiconductor or silicon substrate which is not covered with the three layers mentioned above, to thereby form columnwise lines of n-type impurity diffused layer in the silicon substrate. Subsequently, a field oxide film is grown by using the nitride film on the first polysilicon layer as an oxidation-resistive mask. In this manner, a field oxide film is formed on the n-type impurity diffused region mentioned above. Next, a second polysilicon layer is deposited and patterned with rowwise lines which extend orthogonally to the columnwise stripe-like lines, whereby the first polysilicon layer is so processed as to assume the form of rectangular parallelepiped. Thus, there is realized a floating gate for a memory cell.
With the conventional technique mentioned above, there can be implemented a nonvolatile semiconductor memory device which is constituted by a plurality of memory cells each having a floating gate for storing or accumulating electrons. Among others, the n-type impurity diffused layer formed at each side of the first polysilicon layer serves as a drain or source region for the memory cell and at the same time serves as a data line or a source line shared by the adjacent bits or cells. On the other hand, the second polysilicon layer functions as a word line for the memory cell. As will be appreciated from the above, with the method disclosed in JP-A-56-142675, the memory cell structure can be implemented by using two layers of mask patterns because of simplified processes, wherein the area required for the memory cell can be reduced.
In a memory cell realized by the conventional technique mentioned above, it is however noted that because the surface of the silicon substrate which is not covered with the oxidation-resistive nitride film overlying the first polysilicon layer which forms the floating gate is oxidized to form the field oxide film, wherein the field oxide film is directly brought into contact with the first polysilicon layer. As a consequence, the field oxide film encroaches upon the gate insulation film region under the influence of the field oxidation, increasing thereby the thickness of the gate oxide film at distal or end portions thereof, which results in that the thickness of the gate oxide film formed immediately underneath the floating gate becomes different between the source region and the drain region.
In the nonvolatile semiconductor memory devices known heretofore, the n-type impurity doped before the field oxidation is diffused transversely into the channel more deeply than the region of the gate oxide film having the thickened end portions. More specifically, because the drain region constituted by the n-type diffused layer region bulges outwardly underneath the gate oxide film region having a substantially uniform thickness, thickening of the gate oxide film at the distal end portions of the gate region exerts substantially no adverse influence to the electron injection/discharge characteristic of the floating gate.
In recent years, in accompanying to a trend for implementation of the memory cells in finer and finer structure to such extent that the gate length becomes shorter than 0.4 micron inclusive, a shallow junction with the diffused layer is indispensably required. Such being the circumstances, unless the diffused drain region extends transversely or laterally about 0.1 micron, it is difficult to realize the memory operations in a satisfactory manner. Thus, in the nonvolatile semiconductor memory device disclosed in JP-A-56-142675 in which the region of the gate oxide film thickened due to the field oxidation has a thickness on the order of 0.1 micron, it is difficult to form the drain region so as to underlie immediately beneath the gate oxide film having a uniform thickness. As a result of this, there arise the problems mentioned below.
In the nonvolatile semiconductor memory device, injection/discharge of electrons to/from the floating gate is realized by making use of the hot electron phenomenon and the tunnel phenomenon which per se are known in the art. It is however noted that the electron injection/discharge characteristics based on the hot electron/tunnel phenomena are very susceptible to the influence of the thickness of the gate oxide film. Consequently, when the drain region is formed in overlapping the thickened region of the gate oxide film, the electron injection/discharge characteristics undergo deterioration which is ascribable to the thickening of the gate oxide film. In addition, due to variance or dispersion in the extent of ingression of the field oxide film, the electron injection/discharge characteristics undergo variations, which in turn incurs variations or differences in the programming voltage as well as the erase voltage from one to another memory cell, making it practically difficult or impossible to set the internal voltage for the nonvolatile semiconductor memory device.
In the nonvolatile semiconductor memory device manufactured according to the hitherto known method mentioned above, the n-type impurity diffused layer is formed between the adjacent memory cells such that the data wire and the source wire can be shared by the adjacent memory cells. However, according to the memory cell operating method disclosed, for example, in JP-A-3-219496 (Japanese Unexamined Patent Application Publication No. 219496/1991), data writing operation is performed simultaneously or en bloc for a plurality of memory cells. It is desirable to isolate the data line and the source line between the adjacent memory cells. In order to separate the metal layers for the diffused regions, the n-type impurity diffused layers which are to constitute the source region and the drain region, respectively, must be formed separately from each other by using a patterned photoresist layer as a mask. In that case, the width of the columnwise lines of the n-type impurity diffused region is determined by the mask alignment between the nitride film or polysilicon layer and the photoresist. This in turn means that variation in the mask alignment provides a cause for variation in the resistance value of the n-type impurity diffused layer. Needless to say, variation in the resistance value mentioned above in turn provides a cause for variation in the data read current, which thus presents a problem in implementation of the memory cell having the data wire separated.